I am a Computer Science engineer specializing in hardware-software co-design, machine learning systems, and high-performance algorithmic engineering. Currently pursuing an M.Sc. in Machine Learning at Poznań University of Technology, with a foundation in rigorous competitive programming and production-grade cloud infrastructure.

Education

M.Sc. in Computer Science (Machine Learning)
Poznań University of Technology

First semester GPA: 4.9 / 5.0. Conducting master's thesis research in Neurosymbolic AI, focusing on scene decomposition, discrete tokenization, and vector quantization under the supervision of Prof. Krzysztof Krawiec.

B.Eng. (Inżynier) in Computer Science
Poznań University of Technology

Graduated Summa Cum Laude (Bardzo dobry z wyróżnieniem).
Overall GPA: 4.89/5.0. Diploma Exam: 5.0/5.0. Thesis Grade: 5.0/5.0.
Member of GHOST (Group of Horribly Optimistic Statisticians).

Erasmus+ Exchange Student
University of Zagreb (FER)

GPA: 4.66/5.0. Completed master's-level coursework including Deep Learning, Introduction to Data Science, Machine Learning 1, and Quantum Computing.

Advanced Mathematics (POMOST Track)
Adam Mickiewicz University

Completed rigorous university mathematics coursework beyond the standard engineering curriculum, including Linear Algebra 2 and Mathematical Analysis with Applications 2.

Standardized Testing & Competitions

Certifications

Academic Research & Publications

Acceleration of the Prefiltering and Alignment Phases in MMseqs2 Using the Processing-in-Memory Approach
Presented at MCCSys Workshop · Raleigh, North Carolina

Biological sequence search is fundamentally bottlenecked by DRAM memory bandwidth. For my bachelor's thesis, I designed a hardware acceleration architecture that offloads memory-intensive prefiltering and alignment kernels directly into UPMEM Processing-in-Memory (PIM) DPUs.

This work was accepted and presented at the ISCA 2026 MCCSys workshop. Hardware access for feasibility research and benchmarking was graciously provided by Prof. Onur Mutlu's SAFARI group.

[ ISCA 2026 MCCSys Presentation · Processing-in-Memory UPMEM Architecture ]
Master's Thesis Research: Neurosymbolic AI
Poznań University of Technology · Supervisor: Prof. Krzysztof Krawiec

Investigating neurosymbolic scene decomposition and visual reasoning based on the DVP/ASR architecture family. Researching discrete tokenization, vector quantization (VQ), Minimum Description Length (MDL) priors, and differentiable rendering pipelines for scene representation.

Professional Engineering Experience

Software Engineer (.NET & DevOps)
LST-Soft Sp. z o.o.

Over two years of full-stack and infrastructure engineering, culminating in a complete 8-hour technical handover presentation regarding system architecture upon departure.

  • Autonomous Routing Engine: Architected an exact Vehicle Routing Problem with Time Windows (VRPTW) pipeline integrating VROOM and OSRM to replace heuristic approximations.
  • Kubernetes & Observability: Built and managed internal Kubernetes clusters (3-node dev cluster + external geo-services cluster). Deployed self-hosted Photon geo-services with automated nightly data syncs. Introduced Prometheus & Grafana for real-time observability.
  • Legacy Modernization: Refactored the core C# backend providing logistics integration for Poland's largest internet electronics manufacturer. Successfully removed 3,000 lines of dead code (from 15k to 12k) from a 15-year-old codebase with zero downtime.
  • CI/CD Pipelines: Engineered Jenkins CI/CD pipelines for automated compilation, cryptographic software signing, and customer installation package generation.

Selected Technical Projects

SceneGenerator & CUDA Optimization

Optimized a CLEVR synthetic scene generation pipeline. Profiled and eliminated CPU-side bottlenecks, enabling 100% GPU utilization and reducing rendering time to 5ms per 224x224 image. This pipeline was utilized in a final computer vision study.

Heterogeneous Knapsack Optimization

Multi-paradigm solvers for the 2-Constraint Knapsack problem. Combined OpenMP CPU fine-grained parallelism with a custom CUDA-accelerated fitness evaluation kernel.

Distributed Mutex (Ricart–Agrawala)

High-performance distributed mutual exclusion implementation using OpenMPI message passing and C++17 thread-safe atomics for local state synchronization.